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? 2014-2015 microchip technology inc. ds20005367b-page 1 mcp6v61/1u/2/4 features high dc precision: -v os drift: 15 nv/c (maximum, v dd =5.5v) -v os : 8 v (maximum) -a ol : 125 db (minimum, v dd =5.5v) - psrr: 117 db (minimum, v dd =5.5v) - cmrr: 120 db (minimum, v dd =5.5v) -e ni : 0.54 v p-p (typical), f = 0.1 hz to 10 hz -e ni : 0.17 v p-p (typical), f = 0.01 hz to 1 hz enhanced emi protection: - electromagnetic interference rejection ratio (emirr) at 1.8 ghz: 101 db low power and supply voltages: -i q : 80 a/amplifier (typical) - wide supply voltage range: 1.8v to 5.5v small packages: - singles in sc70, sot-23 - duals in msop-8, 2x3 tdfn - quads in tssop-14 easy to use: - rail-to-rail input/output - gain bandwidth product: 1 mhz (typical) - unity gain stable extended temperature range: -40c to +125c typical applications portable instrumentation sensor conditioning temperature measurement dc offset correction medical instrumentation design aids spice macro models filterlab ? software microchip advanced part selector (maps) analog demonstration and evaluation boards application notes related parts mcp6v11/1u/2/4: zero-drift, low power mcp6v31/1u/2/4: zero-drift, low power mcp6v71/1u/2/4: zero-drift, 2 mhz mcp6v81/1u: zero-drift, 5 mhz mcp6v91/1u: zero-drift, 10 mhz general description the microchip technology inc. mcp6v61/1u/2/4 family of operational amplifiers provides input offset voltage correction for very low offset and offset drift. these devices have a gain bandwidth product of 1 mhz (typical). they are unity-gain stable, have virtually no 1/f noise and have good power supply rejection ratio (psrr) and common mode rejection ratio (cmrr). these products operate with a single supply voltage as low as 1.8v, while drawing 80 a/amplifier (typical) of quiescent current. the microchip technology inc. mcp6v61/1u/2/4 op amps are offered in single (mcp6v61 and mcp6v61u), dual (mcp6v62) and quad (mcp6v64) packages. they were designed using an advanced cmos process. package types v in + v ss v in C 1 2 3 5 4 v dd v out mcp6v61 sot-23 mcp6v61u sc70, sot-23 v in C v ss v out 1 2 3 5 4 v dd v in + v ina + v ina C v ss 1 2 3 4 8 7 6 5 v outa v dd v outb v inb C v inb + mcp6v62 msop mcp6v62 23 tdfn * v ina + v ina C v ss v outb v inb C 1 2 3 4 8 7 6 5 v inb + v dd v outa ep 9 * includes exposed thermal pad (ep); see ta b l e 3 - 1 . v ina + v ina C v dd 1 2 3 4 14 13 12 11 v outa v outd v ind C v ind + v ss mcp6v64 tssop v inb C v inb + v outb 5 6 7 10 9 8 v inc + v inc C v outc mcp6v61u sc70, sot-23 v in C v ss v out 1 2 3 5 4 v dd v in + 80 a, 1 mhz zero-drift op amps downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 2 ? 2014-2015 microchip technology inc. typical application circuit figures 1 and 2 show input offset voltage versus ambi- ent temperature for different power supply voltages. figure 1: input offset voltage vs. ambient temperature with v dd =1.8v. figure 2: input offset voltage vs. ambient temperature with v dd =5.5v. as seen in figures 1 and 2 , the mcp6v61/1u/2/4 op amps have excellent performance across temperature. the input offset voltage temperature drift (tc 1 ) shown is well within the specified maximum values of 15 nv/c at v dd = 5.5v and 30 nv/c at v dd =1.8v. this performance supports applications with stringent dc precision requirements. in many cases, it will not be necessary to correct for temperature effects (i.e., calibrate) in a design. in the other cases, the correction will be small. u 1 mcp6xxx offset voltage correction for power driver c 2 r 2 r 1 r 3 v dd /2 r 4 v in v out r 2 v dd /2 r 5 u 2 mcp6v61 -+ -+ -8 -6 -4 -2 0 2 4 6 8 -50 -25 0 25 50 75 100 125 input offset voltage (v) ambient temperature ( c) 28 samples v dd = 1.8v -8 -6 -4 -2 0 2 4 6 8 -50 -25 0 25 50 75 100 125 input offset voltage (v) temperature ( c) 28 samples v dd = 5.5v downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 3 mcp6v61/1u/2/4 1.0 electrical characteristics 1.1 absolute maximum ratings ? v dd Cv ss .............................................................................................................................. ...................................6.5v current at input pins ......................................................................................................... .....................................2 ma analog inputs (v in + and v in -) ( note 1 ) .....................................................................................v ss C 1.0v to v dd +1.0v all other inputs and outputs .................................................................................................. ..v ss C 0.3v to v dd +0.3v difference input voltage ...................................................................................................... ...........................|v dd Cv ss | output short circuit current .................................................................................................. ......................... continuous current at output and supply pins ............................................................................................. ......................... 30 ma storage temperature ........................................................................................................... ..................-65c to +150c maximum junction temperature .................................................................................................. ........................ +150c esd protection on all pins (hbm, cdm, mm) mcp6v61/1u ???????????????????????????????????????????????????????????????????????????????????????????????????? ??????????????????????????????????????????????? ? 4kv,1.5kv,400v mcp6v62/4 ???????????????????????????????????????????????????????????????????????????????????????????????????? ?????????????????????????????????????????????????? ? 4kv,1.5kv,300v note 1: see section 4.2.1 ?rail-to-rail inputs? . 1.2 specifications ?notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 1-1: dc electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l = 30 pf (refer to figures 1-4 and 1-5 ). parameters sym. min. typ. max. units conditions input offset input offset voltage v os -8 +8 v t a =+25c input offset voltage drift with temperature (linear temp. co.) tc 1 -30 +30 nv/c t a = -40 to +125c, v dd =1.8v ( note 1 ) tc 1 -15 +15 nv/c t a = -40 to +125c, v dd =5.5v ( note 1 ) input offset voltage quadratic te m p . c o . tc 2 - 3 0p v / c 2 t a = -40 to +125c v dd =1.8v tc 2 - 6 p v / c 2 t a = -40 to +125c v dd =5.5v input offset voltage aging ? v os 0.45 v 408 hours life test at +150, measured at +25c. power supply rejection ratio psrr 117 134 db note 1: for design guidance only; not tested. 2: figure 2-19 shows how v cml and v cmh changed across temperature for the first production lot. 3: parts with date codes prior to september 2015 (week code 27) were screened to a +5 na maximum limit. 4: parts with date codes prior to september 2015 (week code 27) were screened to 2 na minimum/maxi- mum limits. downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 4 ? 2014-2015 microchip technology inc. input bias current and impedance input bias current i b -50 1 +50 pa input bias current across temperature i b + 2 0p a t a =+85c i b 0+ 0 . 2+ 1 . 5n a t a = +125c ( note 3 ) input offset current i os -200 60 +200 pa input offset current across temperature i os 5 0p a t a =+85c i os -800 50 +800 pa t a = +125c ( note 4 ) common mode input impedance z cm 1 0 13 ||8 ? ||pf differential input impedance z diff 1 0 13 ||8 ? ||pf common mode common mode input voltage range low v cml v ss -0.2 v note 2 common mode input voltage range high v cmh v dd +0.3 v note 2 common mode rejection ratio cmrr 111 128 db v dd =1.8v, v cm = -0.2v to 2.1v ( note 2 ) cmrr 120 134 db v dd =5.5v, v cm = -0.2v to 5.8v ( note 2 ) open-loop gain dc open-loop gain (large signal) a ol 114 146 db v dd =1.8v, v out = 0.3v to 1.6v a ol 125 158 db v dd =5.5v, v out = 0.3v to 5.3v output minimum output voltage swing v ol v ss v ss +35 v ss +121 mv r l =2k ? , g = +2, 0.5v input overdrive v ol v ss +3.5 mv r l =20k ? , g = +2, 0.5v input overdrive maximum output voltage swing v oh v dd -121 v dd C35 v dd mv r l =2k ? , g = +2, 0.5v input overdrive v oh v dd C3.5 mv r l =20k ? , g = +2, 0.5v input overdrive output short circuit current i sc 7m a v dd =1.8v i sc 2 3m a v dd =5.5v power supply supply voltage v dd 1.8 5.5 v quiescent current per amplifier i q 40 80 130 a i o = 0 power-on reset (por) trip voltage v por 0.9 1.6 v table 1-1: dc electrical specifications (continued) electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l = 30 pf (refer to figures 1-4 and 1-5 ). parameters sym. min. typ. max. units conditions note 1: for design guidance only; not tested. 2: figure 2-19 shows how v cml and v cmh changed across temperature for the first production lot. 3: parts with date codes prior to september 2015 (week code 27) were screened to a +5 na maximum limit. 4: parts with date codes prior to september 2015 (week code 27) were screened to 2 na minimum/maxi- mum limits. downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 5 mcp6v61/1u/2/4 table 1-2: ac electrical specifications electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +1.8v to +5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l = 30 pf (refer to figures 1-4 and 1-5 ). parameters sym. min. typ. max. units conditions amplifier ac response gain bandwidth product gbwp 1 mhz slew rate sr 0.45 v/s phase margin pm 60 c g = +1 amplifier noise response input noise voltage e ni 0.17v p-p f=0.01hz to 1hz e ni 0.54v p-p f = 0.1 hz to 10 hz input noise voltage density e ni 2 6n v / hz f < 2 khz input noise current density i ni 5f a / hz amplifier distortion ( note 1 ) intermodulation distortion (ac) imd 48 v pk v cm tone = 50 mv pk at 1 khz, g n =11, rti amplifier step response start-up time t str 250 s g = +1, 0.1% v out settling ( note 2 ) offset correction settling time t stl 3 0 sg = + 1 , v in step of 2v, v os within 100 v of its final value output overdrive recovery time t odr 60 s g = -10, 0.5v input overdrive to v dd /2, v in 50% point to v out 90% point ( note 3 ) emi protection emi rejection ratio emirr 80 db v in =0.1v pk , f = 400 mhz 9 6 v in =0.1v pk , f = 900 mhz 1 0 1 v in =0.1v pk , f = 1800 mhz 1 0 2 v in =0.1v pk , f = 2400 mhz note 1: these parameters were characterized using the circuit in figure 1-6 . in figures 2-40 and 2-41 , there is an imd tone at dc, a residual tone at 1 khz and other imd tones and clock tones. imd is referred to input (rti). 2: high gains behave differently; see section 4.3.3 ?offset at power-up? . 3: t stl and t odr include some uncertainty due to clock edge timing. table 1-3: temperature specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v dd = +1.8v to +5.5v, v ss =gnd parameters sym. min. typ. max. units conditions temperature ranges specified temperature range t a -40 +125 c operating temperature range t a -40 +125 c note 1 storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 5ld-sc70 ? ja 2 0 9 c / w thermal resistance, 5ld-sot-23 ? ja 2 0 1 c / w thermal resistance, 8l-2x3 tdfn ? ja 5 3 c / w thermal resistance, 8l-msop ? ja 2 1 1 c / w thermal resistance, 14l-tssop ? ja 1 0 0 c / w note 1: operation must not cause t j to exceed the maximum junction temperature specification (+150c). downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 6 ? 2014-2015 microchip technology inc. 1.3 timing diagrams figure 1-1: amplifier start-up. figure 1-2: offset correction settling time. figure 1-3: output overdrive recovery. 1.4 test circuits the circuits used for most dc and ac tests are shown in figures 1-4 and 1-5 . lay the bypass capacitors out as discussed in section 4.3.10 ?supply bypassing and filtering? . r n is equal to the parallel combination of r f and r g to minimize bias current effects. figure 1-4: ac and dc test circuit for most non-inverting gain conditions. figure 1-5: ac and dc test circuit for most inverting gain conditions. the circuit in figure 1-6 tests the inputs dynamic behavior (i.e., imd, t str , t stl and t odr ). the potentiometer balances the resistor network (v out should equal v ref at dc). the op amps common mode input voltage is v cm =v in /2. the error at the input (v err ) appears at v out with a noise gain of 10 v/v. figure 1-6: test circuit for dynamic input behavior. v dd v out 1.001(v dd /3) 0.999(v dd /3) t str 0v 1.8v to 5.5v 1.8v v in v os v os +100v v os C100v t stl v in v out v dd v ss t odr t odr v dd /2 v dd r g r f r n v out v in v dd /3 1f c l r l v l 100 nf r iso mcp6v6x + - v dd r g r f r n v out v dd /3 v in 1f c l r l v l 100 nf r iso mcp6v6x + - v dd v out 1f c l v l r iso 11.0 k ? 249 ? 11.0 k ? 500 ? v in v ref =v dd /3 0.1% 0.1% 25 turn 100 k ? 100 k ? 0.1% 0.1% r l 0 ? 30 pf open 100 nf 1% mcp6v6x downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 7 mcp6v61/1u/2/4 2.0 typical performance curves note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. 2.1 dc input precision figure 2-1: input offset voltage. figure 2-2: input offset voltage drift. figure 2-3: input offset voltage quadratic temp. co. figure 2-4: input offset voltage vs. power supply voltage with v cm =v cml . figure 2-5: input offset voltage vs. power supply voltage with v cm =v cmh . figure 2-6: input offset voltage vs. output voltage with v dd =1.8v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 percentage of occurences input offset voltage (v) 28 samples t a = 25oc v dd = 1.8v v dd = 5.5v 0% 10% 20% 30% 40% 50% 60% -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 percentage of occurrences input offset voltage drift; tc 1 (nv/ c) 28 samples t a = -40 c to +125 c v dd = 1.8v v dd = 5.5v 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% -80 -60 -40 -20 0 20 40 60 80 percentage of occurrences input offset voltage quadratric temp co; tc 2 (pv/ c 2 ) 28 samples t a = -40 c to +125 c v dd = 1.8v v dd = 5.5v -8 -6 -4 -2 0 2 4 6 8 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 input offset voltage (v) power supply voltage (v) representative part v cm = v cml t a = -40c t a = +25c t a = +85c t a = +125c -8 -6 -4 -2 0 2 4 6 8 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 input offset voltage (v) power supply voltage (v) representative part v cm = v cmh t a = -40c t a = +25c t a = +85c t a = +125c -8 -6 -4 -2 0 2 4 6 8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 input offset voltage (v) output voltage (v) representative part v dd = 1.8v t a = - 40c t a = +25c t a = +85c t a = +125c downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 8 ? 2014-2015 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. figure 2-7: input offset voltage vs. output voltage with v dd =5.5v. figure 2-8: input offset voltage vs. common mode voltage with v dd =1.8v. figure 2-9: input offset voltage vs. common mode voltage with v dd =5.5v. figure 2-10: common mode rejection ratio. figure 2-11: power supply rejection ratio. figure 2-12: dc open-loop gain. -8 -6 -4 -2 0 2 4 6 8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input offset voltage (v) power supply voltage (v) representative part v dd = 5.5v t a = - 40c t a = +25c t a = +85c t a = +125c -8 -6 -4 -2 0 2 4 6 8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 input offset voltage (v) common mode input voltage (v) representative part v dd = 1.8v t a = +125c t a = +85c t a = +25c t a = - 40c -8 -6 -4 -2 0 2 4 6 8 -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input offset voltage (v) common mode input voltage (v) representative part v dd = 5.5v t a = +125c t a = +85c t a = +25c t a = - 40c 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 percentage of occurrences 1/cmrr (v/v) 617 samples t a = +25c v dd = 1.8v v dd = 5.5v tester data 0% 10% 20% 30% 40% 50% 60% 70% 80% -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 percentage of occurrences 1/psrr (v/v) 617 samples t a = +25oc tester data 0% 10% 20% 30% 40% 50% 60% 70% -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 percentage of occurrences 1/a ol (v/v) 617 samples t a = +25c v dd = 5.5v v dd = 1.8v tester data downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 9 mcp6v61/1u/2/4 note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. figure 2-13: cmrr and psrr vs. ambient temperature. figure 2-14: dc open-loop gain vs. ambient temperature. figure 2-15: input bias and offset currents vs. common mode input voltage with t a = +85c. figure 2-16: input bias and offset currents vs. common mode input voltage with t a = +125c. figure 2-17: input bias and offset currents vs. ambient temperature with v dd =5.5v. figure 2-18: input bias current vs. input voltage (below v ss ). 110 120 130 140 150 160 -50 -25 0 25 50 75 100 125 cmrr, psrr (db) ambient temperature (c) psrr cmrr @ v dd = 5.5v @ v dd = 1.8v 110 120 130 140 150 160 170 -50 -25 0 25 50 75 100 125 dc open-loop gain (db) ambient temperature (c) v dd = 5.5v v dd =1.8v -500 -400 -300 -200 -100 0 100 200 300 400 500 -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input bias and offset currents (pa) input common mode voltage (v) in p ut bias current input offset current v dd = 5.5 v t a = +85 oc -500 -400 -300 -200 -100 0 100 200 300 400 500 -0.5 0.00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input bias and offset currents (pa) input common mode voltage (v) in p ut bias current input offset current v dd = 5.5 v t a = +125 oc 2535 45 55 65 75 85 95 105115 125 input bias, offset currents (a) ambient temperature (c) in p ut bias current input offset current v dd = 5.5 v 1n 100 p 10 p 1 p 0.1 p 0.001 0.01 0.1 1 10 100 1000 10000 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input current magnitude (a) input voltage (v) 1m 10 100n 10n 1n t a = +125 c t a = +85 c t a = +25 c t a = -40 c 100 1 100p downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 10 ? 2014-2015 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. 2.2 other dc voltages and currents figure 2-19: input common mode voltage headroom (range) vs. ambient temperature. figure 2-20: output voltage headroom vs. output current. figure 2-21: output voltage headroom vs. ambient temperature. figure 2-22: output short circuit current vs. power supply voltage. figure 2-23: supply current vs. power supply voltage. figure 2-24: power-on reset trip voltage. -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 -50 -25 0 25 50 75 100 125 input common mode voltage headroom (v) ambient temperature ( c) upper (v cmh C v dd ) lower (v cml C v ss ) 1 wafer lot 1 10 100 1000 0.1 1 10 output voltage headroom (mv) output current magnitude (ma) v dd = 5.5v v dd = 1.8v v dd C v oh v ol C v ss 0 10 20 30 40 50 60 70 80 90 -50 -25 0 25 50 75 100 125 output headroom (mv) ambient temperature (c) v dd C v oh v dd = 5.5v v dd C v oh v ol C v ss v dd = 1.8v r l = 2 k -40 -30 -20 -10 0 10 20 30 40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 output short circuit current (ma) power supply voltage (v) t a = +125 c t a = +85 c t a = +25 c t a = -40 c t a = +125 c t a = +85 c t a = +25 c t a = -40 c representative part 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 quiescent current (a/amplifier) power supply voltage (v) t a = +125 c t a = +85 c t a = +25 c t a = -40 c representative part 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 percentage of occurrences por trip voltage (v) 615 samples 1 wafer lot t a = +25 c downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 11 mcp6v61/1u/2/4 note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. figure 2-25: power-on reset voltage vs. ambient temperature. 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 -50 -25 0 25 50 75 100 125 por trip voltage (v) ambient temperature (c) 615 samples 1 wafer lot downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 12 ? 2014-2015 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. 2.3 frequency response figure 2-26: cmrr and psrr vs. frequency. figure 2-27: open-loop gain vs. frequency with v dd =1.8v. figure 2-28: open-loop gain vs. frequency with v dd =5.5v. figure 2-29: gain bandwidth product and phase margin vs. ambient temperature. figure 2-30: gain bandwidth product and phase margin vs. common mode input voltage. figure 2-31: gain bandwidth product and phase margin vs. output voltage. 10 20 30 40 50 60 70 80 90 100 110 120 130 140 10 100 1000 10000 100000 cmrr, psrr (db) frequency (hz) 10 100 1k 10k 100k cmrr psrr+ psrr- representative part -270 -240 -210 -180 -150 -120 -90 -60 -30 -20 -10 0 10 20 30 40 1.e+04 1.e+05 1.e+06 1.e+07 f (hz) open-loop phase ( ) open-loop gain (db) open-loop gain open-loop phase v dd = 1.8v c l = 30 pf 10k 100k 1m 10m -270 -240 -210 -180 -150 -120 -90 -60 -30 -20 -10 0 10 20 30 40 1.e+04 1.e+05 1.e+06 1.e+07 f (hz) open-loop phase ( ) open-loop gain (db) open-loop gain open-loop phase v dd = 5.5v c l = 30 pf 10k 100k 1m 10m 0 10 20 30 40 50 60 70 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -50 -25 0 25 50 75 100 125 gain bandwidth product (mhz) ambient temperature (c) gbwp pm v dd = 1.8v phase margin ( ) v dd = 5.5v 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -101234567 phase margin () gain bandwith product (mhz) common mode input voltage (v) v dd = 5.5v v dd = 1.8v pm gbwp 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 0123456 phase margin () gain bandwidth product (mhz) output voltage (v) v dd = 5.5v pm gbwp v dd = 1.8v downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 13 mcp6v61/1u/2/4 note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. figure 2-32: closed-loop output impedance vs. frequency with v dd =1.8v. figure 2-33: closed-loop output impedance vs. frequency with v dd =5.5v. figure 2-34: maximum output voltage swing vs. frequency. figure 2-35: emirr vs. frequency. figure 2-36: emirr vs. input voltage. figure 2-37: channel-to-channel separation vs. frequency. 10 100 1000 10000 100000 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 closed-loop output impedance ( ) frequency (hz) g n = 101 v/v g n = 11 v/v g n = 1 v/v 1k 10k 100k 1m 10m v dd = 1.8v 1k 100k 10k 10 100 1000 10000 100000 1.0e+03 1.0e+04 1.0e+05 1.0e+06 1.0e+07 closed-loop output impedance ( ) frequency (hz) g n = 101 v/v g n = 11 v/v g n = 1 v/v 1k 10k 100k 1m 10m v dd = 5.5v 100k 10k 1k 0.1 1 10 1000 10000 100000 1000000 output voltage swing (v p-p ) frequency (hz) v dd = 1.8v v dd = 5.5v 1k 10k 100k 1m 0 10 20 30 40 50 60 70 80 90 100 110 120 10 100 1000 10000 emirr (db) frequency (hz) 10m 10 0m 1g 10g v in = 100 mv pk v dd = 5.5v 0 20 40 60 80 100 120 0.01 0.1 1 10 emirr (db) input voltage (v pk ) emirr @ 2400 mhz emirr @ 1800 mhz emirr @ 900 mhz emirr @ 400 mhz v dd = 5.5v 60 70 80 90 100 110 120 130 1.e+04 1.e+05 1.e+06 channel-to-channel separation; rti (db) frequency (hz) 10k 100k 1m v dd = 5.5v v dd = 1.8v downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 14 ? 2014-2015 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. 2.4 input noise and distortion figure 2-38: input noise voltage density and integrated input noise voltage vs. frequency. figure 2-39: input noise voltage density vs. input common mode voltage. figure 2-40: intermodulation distortion vs. frequency with v cm disturbance (see figure 1-6 ). figure 2-41: inter-modulation distortion vs. frequency with v dd disturbance (see figure 1-6 ). figure 2-42: input noise vs. time with 1 hz and 10 hz filters and v dd =1.8v. figure 2-43: input noise vs. time with 1 hz and 10 hz filters and v dd =5.5v. 1 10 100 1000 1 10 100 1000 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 frequency (hz) integrated input noise voltage; e ni (v p-p ) input noise voltage density; e ni (nv/ hz) vdd = 1.8v vdd = 5.5v e ni e ni (0 hz to f) 1 10 100 1k 10k 100k v dd = 1.8v v dd = 5.5v 0 5 10 15 20 25 30 35 -1 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 input noise voltage density q9+] common mode input voltage (v) v dd = 1.8v v dd = 5.5v f < 2 khz 1.e-8 1.e-7 1.e-6 1.e-5 1.e-4 1.e-3 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 imd spectrum, rti (v pk ) frequency (hz) 1 10 100 1k 10k 100k 1m 100 10 1 100n 10n g = 11 v/v v cm tone = 100 mv pk , f = 1 khz dc tone residual 1 khz tone (due to resistor mismatch) f = 64 hz f = 2 hz v dd = 1.8v v dd = 5.5v 1.e-8 1.e-7 1.e-6 1.e-5 1.e-4 1.e-3 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 imd spectrum, rti (v pk ) frequency (hz) 1 10 100 1k 10k 100k 1m 100 10 1 100n 10n g = 11 v/v v dd tone = 100 mv pk , f = 1 khz dc tone residual 1 khz tone f = 64 hz f = 2 hz v dd = 1.8v v dd = 5.5v ,qsxw1rlvh9rowdjhh ql w ?9gly 7lphv 9 '' 9 13%: +] 13%: +] 0 102030405060708090 100 input noise voltage; e ni (t) (0.2 v/div) time (s) v dd = 5.5v npbw = 10 hz npbw = 1 hz downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 15 mcp6v61/1u/2/4 note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. 2.5 time response figure 2-44: input offset voltage vs. time with temperature change. figure 2-45: input offset voltage vs. time at power-up. figure 2-46: the mcp6v61/1u/2/4 family shows no input phase reversal with overdrive. figure 2-47: non-inverting small signal step response. figure 2-48: non-inverting large signal step response. figure 2-49: inverting small signal step response. -120 -100 -80 -60 -40 -20 0 20 40 60 80 -10 -5 0 5 10 15 20 25 30 35 40 0 1020 30 40 50 60 70 80 90 100110 120 pcb temperature (oc) input offset voltage (v) time (s) v dd = 1.8v t pcb v os temperature increased by using heat gun for 5 seconds. v dd = 5.5v -2 -1 0 1 2 3 4 5 6 -10 -5 0 5 10 15 20 25 30 012345678910 power supply voltage (v) input offset voltage (mv) time (ms) v dd = 5.5v g = 1 v/v v os v dd por trip point v dd bypass = 1 f -1 0 1 2 3 4 5 6 input/output voltages (v) time (0.1 ms/div) v dd = 5.5 v g = 1 v/v v out v in 0123456789 10 output voltage (50 mv/div) time (s) v dd = 5.5v g = +1 v/v 0 1 2 3 4 5 6 0 5 10 15 20 25 30 35 40 45 50 output voltage (v) time (s) v dd = 5.5 v g = +1 v/v 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 output voltage (20 mv/div) time (s) v dd = 5.5 v g = -1 v/v downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 16 ? 2014-2015 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +1.8v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =20k ? to v l and c l =30pf. figure 2-50: inverting large signal step response. figure 2-51: slew rate vs. ambient temperature. figure 2-52: output overdrive recovery vs. time with g = -10 v/v. figure 2-53: output overdrive recovery time vs. inverting gain. 0 1 2 3 4 5 6 0 5 10 15 20 25 30 35 40 45 50 output voltage (v) time ( s) v dd = 5.5 v g = -1 v/v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 slew rate (v/s) ambient temperature (c) falling edge, v dd = 5.5v falling edge, v dd = 1.8v rising edge, v dd = 5.5v rising edge, v dd = 1.8v -1 0 1 2 3 4 5 6 input and output voltages (v) time (50 s/div) gv in gv in v out v out v dd = 5.5v g = -10 v/v 0.5v overdrive 11 01 0 0 1000 overdrive recovery time (s) inverting gain magnitude (v/v) 100 10 1 0.5v input overdrive 1m 10m v dd = 1.8v v dd = 5.5v t odr , high t odr , low downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 17 mcp6v61/1u/2/4 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . 3.1 analog outputs the analog output pins (v out ) are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs (v in +, v in -, ) are high-impedance cmos inputs with low bias currents. 3.3 power supply pins the positive power supply (v dd ) is 1.8v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. 3.4 exposed thermal pad (ep) there is an internal connection between the exposed thermal pad (ep) and the v ss pin; they must be connected to the same potential on the printed circuit board (pcb). this pad can be connected to a pcb ground plane to provide a larger heat sink. this improves the package thermal resistance ( ja ). table 3-1: pin function table mcp6v61 mcp6v61u mcp6v62 mcp6v64 symbol description sot-23 sot-23, sc-70 23 tdfn msop tssop 14111 v out , v outa output (op amp a) 22441 1v ss negative power supply 31333 v in +, v ina + non-inverting input (op amp a) 43222 v in -, v ina - inverting input (op amp a) 55884v dd positive power supply 555v inb + non-inverting input (op amp b) 666v inb - inverting input (op amp b) 777v outb output (op amp b) 8v outc output (op amp c) 9v inc - inverting input (op amp c) 1 0v inc + non-inverting input (op amp c) 1 2v ind + non-inverting input (op amp d) 1 3v ind - inverting input (op amp d) 1 4v outd output (op amp d) 9 ep exposed thermal pad (ep); must be connected to v ss downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 18 ? 2014-2015 microchip technology inc. 4.0 applications the mcp6v61/1u/2/4 family of zero-drift op amps is manufactured using microchips state-of-the-art cmos process. it is designed for precision applications with requirements for small packages and low power. its low supply voltage and low quiescent current make the mcp6v61/1u/2/4 devices ideal for battery-powered applications. 4.1 overview of zero-drift operation figure 4-1 shows a simplified diagram of the mcp6v61/1u/2/4 zero-drift op amps. this diagram will be used to explain how slow voltage errors are reduced in this architecture (much better v os , ? v os / ? t a (tc 1 ), cmrr, psrr, a ol and 1/f noise). figure 4-1: simplified zero-drift op amp functional diagram. 4.1.1 building blocks the main amplifier is designed for high gain and bandwidth, with a differential topology. its main input pair (+ and - pins at the top left) is used for the higher frequency portion of the input signal. its auxiliary input pair (+ and - pins at the bottom left) is used for the low-frequency portion of the input signal, and corrects the op amps input offset voltage. both inputs are added together internally. the auxiliary amplifier, chopper input switches and chopper output switches provide a high dc gain to the input signal. dc errors are modulated to higher frequencies, while white noise is modulated to low frequency. the low-pass filter reduces high-frequency content, including harmonics of the chopping clock. the output buffer drives external loads at the v out pin (v ref is an internal reference voltage). the oscillator runs at f osc1 = 200 khz. its output is divided by two to produce the chopping clock rate of f chop = 100 khz. the internal power-on reset (por) starts the part in a known good state, protecting against power supply brown-outs. the digital control block controls switching and por events. 4.1.2 chopping action figure 4-2 shows the amplifier connections for the first phase of the chopping clock, and figure 4-3 shows the connections for the second phase. its slow voltage errors alternate in polarity, making the average error small. figure 4-2: first chopping clock phase; equivalent amplifier diagram. figure 4-3: second chopping clock phase; equivalent amplifier diagram. v in + v in C main buffer v out v ref amp. output nc aux. amp. chopper input switches chopper output switches oscillator low-pass filter por digital control + - + - + - + - + - + - v in + v in C main amp. nc aux. amp. low-pass filter + - + - + - + - + - v in + v in C main amp. nc aux. amp. low-pass filter + - + - + - + - + - downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 19 mcp6v61/1u/2/4 4.1.3 intermodulation distortion (imd) these op amps will show intermodulation distortion (imd) products when an ac signal is present. the signal and clock can be decomposed into sine wave tones (fourier series components). these tones interact with the zero-drift circuitrys nonlinear response to produce imd tones at sum and difference frequencies. each of the square wave clocks harmonics has a series of imd tones centered on it. see figures 2-40 and 2-41 . 4.2 other functional blocks 4.2.1 rail-to-rail inputs the input stage of the mcp6v61/1u/2/4 op amps uses two differential cmos input stages in parallel. one operates at low common mode input voltage (v cm , which is approximately equal to v in + and v in - in normal operation) and the other at high v cm . with this topology, the input operates with v cm up to v dd +0.3v and down to v ss C 0.2v, at +25c (see figure 2-19 ). the input offset voltage (v os ) is measured at v cm =v ss C 0.2v and v dd + 0.3v to ensure proper operation. 4.2.1.1 phase reversal the input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. figure 2-46 shows an input voltage exceeding both supplies with no phase inversion. 4.2.1.2 input voltage limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the voltages at the input pins (see section 1.1 ?absolute maximum ratings ?? ). this requirement is independent of the current limits discussed later on. the esd protection on the inputs can be depicted as shown in figure 4-4 . this structure was chosen to protect the input transistors against many (but not all) overvoltage conditions and to minimize input bias current (i b ). figure 4-4: simplified analog input esd structures. the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages well above v dd ; their breakdown voltage is high enough to allow normal operation but not low enough to protect against slow overvoltage (beyond v dd ) events. very fast esd events (that meet the specification) are limited so that damage does not occur. in some applications, it may be necessary to prevent excessive voltages from reaching the op amp inputs; figure 4-5 shows one approach to protecting these inputs. d 1 and d 2 may be small signal silicon diodes, schottky diodes for lower clamping voltages or diode-connected fets for low leakage. figure 4-5: protecting the analog inputs against high voltages. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in C v 1 v dd d 1 v out v 2 d 2 u 1 mcp6v6x + - downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 20 ? 2014-2015 microchip technology inc. 4.2.1.3 input current limits in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents into the input pins (see section 1.1 ?absolute maximum ratings ?? ). this requirement is independent of the voltage limits discussed previously. figure 4-6 shows one approach to protecting these inputs. the r 1 and r 2 resistors limit the possible current in or out of the input pins (and into d 1 and d 2 ). the diode currents will dump onto v dd . figure 4-6: protecting the analog inputs against high currents. it is also possible to connect the diodes to the left of the r 1 and r 2 resistors. in this case, the currents through the d 1 and d 2 diodes need to be limited by some other mechanism. the resistors then serve as in-rush current limiters; the dc current into the input pins (v in + and v in -) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common mode voltage (v cm ) is below ground (v ss ) (see figure 2-18 ). 4.2.2 rail-to-rail output the output voltage range of the mcp6v61/1u/2/4 zero-drift op amps is v dd C 5.9 mv (typical) and v ss + 4.7 mv (typical) when r l =20k ? is connected to v dd /2 and v dd = 5.5v. refer to figures 2-20 and 2-21 for more information. this op amp is designed to drive light loads; use another amplifier to buffer the output from heavy loads. 4.3 application tips 4.3.1 input offset voltage over temperature table 1-1 gives both the linear and quadratic temperature coefficients (tc 1 and tc 2 ) of input offset voltage. the input offset voltage, at any temperature in the specified range, can be calculated as follows: equation 4-1: 4.3.2 dc gain plots figures 2-10 to 2-12 are histograms of the reciprocals (in units of v/v) of cmrr, psrr and a ol , respectively. they represent the change in input offset voltage (v os ) with a change in common mode input voltage (v cm ), power supply voltage (v dd ) and output voltage (v out ). the histograms are based on data taken with the production test equipment and the results reflect the trade-off between accuracy and test time. the actual performance of the devices is typically higher than shown in figures 2-10 to 2-12 . the 1/a ol histogram is centered near 0 v/v because the measurements are dominated by the op amps input noise. the negative values shown represent noise and tester limitations, not unstable behavior. production tests make multiple v os measurements, which validates an op amp's stability; an unstable part would show greater v os variability or the output would stick at one of the supply rails. 4.3.3 offset at power-up when these parts power up, the input offset (v os ) starts at its uncorrected value (usually less than 5 mv). circuits with high dc gain can cause the output to reach one of the two rails. in this case, the time to a valid output is delayed by an output overdrive time (like t odr ) in addition to the start-up time (like t str ). it can be simple to avoid this extra start-up time. reducing the gain is one method. adding a capacitor across the feedback resistor (r f ) is another method. v 1 r 1 v dd d 1 min(r 1 ,r 2 )> v ss ?min(v 1 ,v 2 ) 2ma v out v 2 r 2 d 2 min(r 1 ,r 2 )> max(v 1 ,v 2 )?v dd 2ma u 1 mcp6v6x + - v os t a ?? v os tc 1 ? ttc 2 ? t 2 ++ = where: ? t=t a C25c v os (t a ) = input offset voltage at t a v os = input offset voltage at +25c tc 1 = linear temperature coefficient tc 2 = quadratic temperature coefficient downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 21 mcp6v61/1u/2/4 4.3.4 source resistances the input bias currents have two significant components: switching glitches that dominate at room temperature and below and input esd diode leakage currents that dominate at +85c and above. make the resistances seen by the inputs small and equal. this minimizes the output offset caused by the input bias currents. the inputs should see a resistance on the order of 10 ? to 1 k ? at high frequencies (i.e., above 1 mhz). this helps minimize the impact of switching glitches, which are very fast, on overall performance. in some cases it may be necessary to add resistors in series with the inputs to achieve this improvement in performance. small input resistances may be needed for high gains. without them, parasitic capacitances might cause positive feedback and instability. 4.3.5 source capacitance the capacitances seen by the two inputs should be small. large input capacitances and source resistances, together with high gain, can lead to positive feedback and instability. 4.3.6 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loops phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. these zero-drift op amps have a different output impedance than most op amps, due to their unique topology. when driving a capacitive load with these op amps, a series resistor at the output (r iso in figure 4-7 ) improves the feedback loops phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-7: output resistor, r iso , stabilizes capacitive loads. figure 4-8 gives recommended r iso values for different capacitive loads and gains. the x-axis is the load capacitance (c l ). the y-axis is the resistance (r iso ). g n is the circuits noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n = +2 v/v). figure 4-8: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double check the resulting frequency response peaking and step response overshoot. modify the r iso value until the response is reasonable. bench evaluation is helpful. 4.3.7 stabilizing output loads this family of zero-drift op amps has an output impedance ( figures 2-32 and 2-33 ) that has a double zero when the gain is low. this can cause a large phase shift in feedback networks that have low-impedance near the parts bandwidth. this large phase shift can cause stability problems. figure 4-9 shows that the load on the output is (r l +r iso )||(r f +r g ), where r iso is before the load (like figure 4-7 ). this load needs to be large enough to maintain stability; it should be at least 10 k ? . figure 4-9: output load. r iso c l v out u 1 mcp6v6x + - 1 10 100 1000 10000 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 recommended r iso ( ) normalized load capacitance; c l / ? ? g n (f) g n : 1 v/v10 v/v 100 v/v v dd = 5.5v r l = 20 k 100p 1n 10n 100n 1 r g r f v out u 1 mcp6v6x r l c l + - r iso downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 22 ? 2014-2015 microchip technology inc. 4.3.8 gain peaking figure 4-10 shows an op amp circuit that represents non-inverting amplifiers (v m is a dc voltage and v p is the input) or inverting amplifiers (v p is a dc voltage and v m is the input). the c n and c g capacitances represent the total capacitance at the input pins; they include the op amps common mode input capacitance (c cm ), board parasitic capacitance and any capacitor placed in parallel. the c fp capacitance represents the parasitic capacitance coupling the output and non-inverting input pins. figure 4-10: amplifier with parasitic capacitance. c g acts in parallel with r g (except for a gain of +1 v/v), which causes an increase in gain at high frequencies. c g also reduces the phase margin of the feedback loop, which becomes less stable. this effect can be reduced by either reducing c g or r f ||r g . c n and r n form a low-pass filter that affects the signal at v p . this filter has a single real pole at 1/(2 r n c n ). the largest value of r f that should be used depends on noise gain (see g n in section 4.3.6 ?capacitive loads? ), c g and the open-loop gains phase shift. an approximate limit for r f is: equation 4-2: some applications may modify these values to reduce either output loading or gain peaking (step-response overshoot). at high gains, r n needs to be small in order to prevent positive feedback and oscillations. large c n values can also help. 4.3.9 reducing undesired noise and signals reduce undesired noise and signals with: low bandwidth signal filters: - minimize random analog noise - reduce interfering signals good pcb layout techniques: - minimize crosstalk - minimize parasitic capacitances and inductances that interact with fast switching edges good power supply design: - isolation from other parts - filtering of interference on supply line(s) 4.3.10 supply bypassing and filtering with this family of operational amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm of the pin for good high-frequency performance. these parts also need a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with other low-noise analog parts. in some cases, high-frequency power supply noise (e.g., switched mode power supplies) may cause undue intermodulation distortion with a dc offset shift; this noise needs to be filtered. adding a small resistor into the supply connection can be helpful. 4.3.11 pcb design for dc precision in order to achieve dc precision on the order of 1 v, many physical errors need to be minimized. the design of the printed circuit board (pcb), the wiring and the thermal environment have a strong impact on the precision achieved. a poor pcb design can easily be more than 100 times worse than the mcp6v61/1u/2/4 op amps minimum and maximum specifications. 4.3.11.1 pcb layout any time two dissimilar metals are joined together, a temperature-dependent voltage appears across the junction (the seebeck or thermojunction effect). this effect is used in thermocouples to measure temperature. the following are examples of thermojunctions on a pcb: components (resistors, op amps, ) soldered to a copper pad wires mechanically attached to the pcb jumpers solder joints pcb vias r g r f v out u 1 mcp6v6x c g r n c n v m v p c fp + - r f 10 k ? 3.5 pf c g --------------- g n 2 ? ? ? downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 23 mcp6v61/1u/2/4 typical thermojunctions have temperature-to-voltage conversion coefficients of 1 to 100 v/c (sometimes higher). microchips an1258 ( op amp precision design: pcb layout techniques ) contains in-depth information on pcb layout techniques that minimize thermojunction effects. it also discusses other effects, such as crosstalk, impedances, mechanical stresses and humidity. 4.3.11.2 crosstalk dc crosstalk causes offsets that appear as a larger input offset voltage. common causes include: common mode noise (remote sensors) ground loops (current return paths) power supply coupling interference from the mains (usually 50 hz or 60 hz) and other ac sources can also affect the dc performance. nonlinear distortion can convert these signals to multiple tones, including a dc shift in voltage. when the signal is sampled by an adc, these ac signals can also be aliased to dc, causing an apparent shift in offset. to reduce interference: - keep traces and wires as short as possible - use shielding - use ground plane (at least a star ground) - place the input signal source near the dut - use good pcb layout techniques - use a separate power supply filter (bypass capacitors) for these zero-drift op amps 4.3.11.3 miscellaneous effects keep the resistances seen by the input pins as small and as near to equal as possible to minimize bias current-related offsets. make the (trace) capacitances seen by the input pins small and equal. this is helpful in minimizing switching glitch-induced offset voltages. bending a coax cable with a radius that is too small causes a small voltage drop to appear on the center conductor (the triboelectric effect). make sure the bending radius is large enough to keep the conductors and insulation in full contact. mechanical stresses can make some capacitor types (such as some ceramics) output small voltages. use more appropriate capacitor types in the signal path and minimize mechanical stresses and vibration. humidity can cause electrochemical potential voltages to appear in a circuit. proper pcb cleaning helps, as does the use of encapsulants. 4.4 typical applications 4.4.1 wheatstone bridge many sensors are configured as wheatstone bridges. strain gauges and pressure sensors are two common examples. these signals can be small and the common mode noise large. amplifier designs with high differential gain are desirable. figure 4-11 shows how to interface to a wheatstone bridge with a minimum of components. because the circuit is not symmetric, the adc input is single-ended and there is a minimum of filtering; the cmrr is good enough for moderate common mode noise. figure 4-11: simple design. 4.4.2 rtd sensor the ratiometric circuit in figure 4-12 conditions a two-wire rtd for applications with a limited temperature range. u 1 acts as a difference amplifier with a low-frequency pole. the sensors wiring resistance (r w ) is corrected in firmware. failure (open) of the rtd is detected by an out-of-range voltage. figure 4-12: rtd sensor. v dd rr rr 100r 0.01c adc v dd 0.2r 0.2r 1k ? u 1 mcp6v61 + - + - r f 10 nf adc v dd r n 1.0 f v dd r w r t r b r rtd r g 100 ? 1.00 k ? 4.99 k ? 34.8 k ? 2.00 m ? 10.0 k ? u 1 mcp6v61 r w 10.0 k ? r f 2.00 m ? 10 nf 100 nf + - + - downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 24 ? 2014-2015 microchip technology inc. 4.4.3 offset voltage correction figure 4-13 shows mcp6v61 (u 2 ) correcting the input offset voltage of another op amp (u 1 ). r 2 and c 2 integrate the offset error seen at u 1 s input; the integration needs to be slow enough to be stable (with the feedback provided by r 1 and r 3 ). r 4 and r 5 attenuate the integrators output; this shifts the integrator pole down in frequency. figure 4-13: offset correction. 4.4.4 precision comparator use high gain before a comparator to improve the latters performance. do not use mcp6v61/1u/2/4 as a comparator by itself; the v os correction circuitry does not operate properly without a feedback loop. figure 4-14: precision comparator. u 1 mcp6xxx c 2 r 2 r 1 r 3 v dd /2 r 4 v in v out r 2 v dd /2 r 5 u 2 mcp6v61 + - + - v in r 3 r 2 v dd /2 v out r 5 r 4 r 1 u 1 mcp6v61 u 2 mcp6541 + - + - downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 25 mcp6v61/1u/2/4 5.0 design aids microchip provides the basic design aids needed for the mcp6v61/1u/2/4 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp6v61/1u/2/4 op amps is available on the micro- chip web site at www.microchip.com . this model is intended to be an initial design tool that works well in the op amps linear region of operation over the tem- perature range. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristics curves. 5.2 filterlab ? software microchips filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.microchip.com/filterlab , the filterlab design tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.3 microchip advanced part selector (maps) maps is a software tool that helps efficiently identify microchip devices that fit a particular design requirement. available at no cost from the microchip web site at www.microchip.com/maps , maps is an overall selection tool for microchips product portfolio that includes analog, memory, mcus and dscs. using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase and sampling of microchip parts. 5.4 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help customers achieve faster time to market. for a complete listing of these boards and their corresponding users guides and technical information, visit the microchip web site at www.microchip.com/analog tools . some boards that are especially useful are: mcp6v01 thermocouple auto-zeroed reference design (p/n mcp6v01rd-tcpl) mcp6xxx amplifier evaluation board 1 (p/n ds51667) mcp6xxx amplifier evaluation board 2 (p/n ds51668) mcp6xxx amplifier evaluation board 3 (p/n ds51673) mcp6xxx amplifier evaluation board 4 (p/n ds51681) active filter demo board kit (p/n ds51614) 8-pin soic/msop/tssop/dip evaluation board (p/n soic8ev) 14-pin soic/tssop/dip evaluation board (p/n soic14ev) 5.5 application notes the following microchip application notes are available on the microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. adn003: ?select the right operational amplifier for your filtering circuits? , ds21821 an722: ?operational amplifier topologies and dc specifications? , ds00722 an723: ?operational amplifier ac specifications and applications? , ds00723 an884: ?driving capacitive loads with op amps? , ds00884 an990: ?analog sensor conditioning circuits ? an overview? , ds00990 an1177: ?op amp precision design: dc errors? , ds01177 an1228: ?op amp precision design: random noise , ds01228 an1258: ?op amp precision design: pcb layout techniques? , ds01258 these application notes and others are listed in the design guide: ?signal chain design guide? , ds21825 downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 26 ? 2014-2015 microchip technology inc. 6.0 packaging information 6.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 5-lead sc70 ( mcp6v61u ) example 5-lead sot-23 (mcp6v61, mcp6v61u) example device code mcp6v61t-e/ot aaawy mcp6v61ut-e/ot aaaxy dt56 aaaw4 42256 device code mcp6v61ut-e/lty dtnn 8-lead msop (3x3 mm) (mcp6v62) example 6v62e 542256 downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 27 mcp6v61/1u/2/4 8-lead tdfn (2x3x0.75 mm) (mcp6v62) example 14-lead tssop (4.4 mm) (mcp6v64) example yyww nnn xxxxxxxx acs 542 25 device code mcp6v62t-e/mny acs note: applies to 8-lead 2x3 tdfn. 6v64e/st 1542 256 downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 28 ? 2014-2015 microchip technology inc. 5-lead plastic small outine transistor (lty) [sc70] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technolog drawing c04-083b d b 1 2 3 e1 e 4 5 ee c l a1 aa 2 downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 29 mcp6v61/1u/2/4 5-lead plastic small outine transistor (lty) [sc70] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 30 ? 2014-2015 microchip technology inc. n b e e1 d 1 2 3 e e1 a a1 a2 c l l1 downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 31 mcp6v61/1u/2/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 32 ? 2014-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 33 mcp6v61/1u/2/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 34 ? 2014-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 35 mcp6v61/1u/2/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 36 ? 2014-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 37 mcp6v61/1u/2/4 downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 38 ? 2014-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 39 mcp6v61/1u/2/4 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 40 ? 2014-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 41 mcp6v61/1u/2/4 appendix a: revision history revision b (september 2015) the following is the list of modifications: 1. added new devices to the family: mcp6v62 and mcp6v64, and related information throughout the document. 2. added figure 2-37 . 3. updated table 3-1 in section 3.0 ?pin descriptions? . 4. added markings and specification drawings for the new packages in section 6.0 ?packaging information? . 5. updated the product identification system section with the new packages. revision a (december 2014) original release of this document. downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 42 ? 2014-2015 microchip technology inc. notes: downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 43 mcp6v61/1u/2/4 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp6v61t: single op amp (tape and reel) (sot-23 only) mcp6v61ut: single op amp (tape and reel) (sc70, sot-23) mcp6v62: dual op amp (msop, 2x3 tdfn) mcp6v62t: dual op amp (tape and reel) (msop, 2x3 tdfn) mcp6v64: quad op amp (tssop) mcp6v64t: quad op amp (tape and reel) (tssop) temperature range: e = -40c to +125c (extended) package: lty* = plastic small outline transistor, 5-lead sc70 ot = plastic small outline transistor, 5-lead sot-23 mny* = plastic dual flat, no-lead - 230.75 mm body, 8-lead ms = plastic micro small outline, 8-lead st = plastic thin shrink small outline - 4.4 mm body, 14-lead *y = nickel palladium gold manufacturing designator. only available on the sc70 and tdfn package. part no. ?x /xx package temperature range device [x] (1) tape and reel note 1: tape and reel identifier only appears in the catalog part number description. this identi- fier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. examples: a) mcp6v61t-e/ot: tape and reel, extended temperature, 5ld sot-23 package a) mcp6v61ut-e/lty: tape and reel extended temperature, 5ld sc70 package b) mcp6v61ut-e/ot: tape and reel, extended temperature, 5ld sot-23 package a) mcp6v62-e/ms: extended temperature, 8ld msop package b) mcp6v62t-e/ms: tape and reel, extended temperature, 8ld msop package c) mcp6v62t-e/mny: tape and reel, extended temperature, 8ld 2x3 tdfn package a) mcp6v64-e/st: extended temperature, 14ld tssop package b) mcp6v64t-e/st: tape and reel extended temperature, 14ld tssop package downloaded from: http:///
mcp6v61/1u/2/4 ds20005367b-page 44 ? 2014-2015 microchip technology inc. notes: downloaded from: http:///
? 2014-2015 microchip technology inc. ds20005367b-page 45 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademark of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2014-2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63277-850-5 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified b y dnv == iso/ ts 1 6 9 4 9 == downloaded from: http:///
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